1 ? fn6264.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006-2007. all rights reserved all other trademarks mentioned are the property of their respective owners. isl97634 white led driver with wide pwm dimming range the isl97634 represents an efficient and highly integrated pwm boost led driver that is suitable for 1.8? to 3.5? lcds that employ 2 to 6 white leds for backlighting. with integrated schottky diode, ovp, and wide range of pwm dimming capability, the isl97634 provides a simple, reliable, and flexible solution to the backlight designers. the isl97634 features a wide range of pwm dimming control capability. it allows dimming frequency as low as dc to 32khz beyond audible spectrum. the isl97634 also features a feedback disconnect switch to prevent the output from being modulated by the pwm dimming signal that minimizes system disturbance. the isl97634 is av ailable in the 8 ld tdfn (2mmx3mm) package. there are 14v, 18v, and 26v ovp options that are suitable for 3 leds, 4 leds, and 6 leds backlight applications respectively. the isl97634 is specified for operation over the -40c to +8 5c ambient temperature at input voltage from 2.4v to 5.5v. pinout isl97634 (8 ld tdfn) top view typical application circuit features ? drives up to 6 leds in series ? ovp (14v, 18v, and 26v for 3, 4 and 6 leds applications) ? pwm dimming control from dc to 32khz ? output disconnect switch ? integrated schottky diode ? 2.4v to 5.5v input ? 85% efficiency ? 1.4mhz switching frequency allows small lc ? 1a shutdown current ? internally compensated ? 8 ld tdfn (2mmx3mm) ? pb-free plus anneal available (rohs compliant) applications ? led backlighting for: - cell phones - smartphones -mp3 -pmp - automotive navigation panel - portable gps 2 3 4 1 7 6 5 8 gnd vin pwm/en nc lx vout fbsw fb vin lx fbsw gnd vin pwm/en fb vout nc 10h or 22h ordering information part number (note) part marking tape & reel (qty) package (pb-free) pkg. dwg. # isl97634irt14z-t ele 13? (6k pcs.) 8 ld 2x3 tdfn l8.2x3a isl97634irt14z-tk ele 13? (1k pcs.) 8 ld 2x3 tdfn l8.2x3a isl97634irt18z-t elf 13? (6k pcs.) 8 ld 2x3 tdfn l8.2x3a ISL97634IRT18Z-TK elf 13? (1k pcs.) 8 ld 2x3 tdfn l8.2x3a isl97634irt26z-t elg 13? (6k pcs.) 8 ld 2x3 tdfn l8.2x3a isl97634irt26z-tk elg 13? (1k pcs.) 8 ld 2x3 tdfn l8.2x3a note: intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-f ree peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet april 10, 2007
2 fn6264.2 april 10, 2007 absolute m aximum ratings (t a = +25c) thermal information input voltage ( v in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v lx voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v fbsw voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance ja (c/w) jc (c/w) tdfn package (notes 1, 2). . . . . . . . . 77 12 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/ma x specifications are guaranteed over temper ature of -40c to +85c unless otherwise stated. typ values are for information purposes only at tj = tc = ta = +25c. note: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v in = v pwm/en = 3v parameter description condition min typ max unit v in supply voltage 2.4 5.5 v i in supply current pwm/en = 3v, enabled, not switching 0.8 1.5 ma pwm/en = 0v, disabled 1 a f sw switching frequency 1,300 1,450 1,600 khz dmax maximum switching duty cycle 90 95 % i lim lx current 400 470 ma r sw(lx) lx switch on-resistance ilx = 100ma 900 m ileak lx switch leakage current vlx = 28v 0.01 1 a vfb feedback voltage 90 95 100 mv ifb fb pin bias current vfb = 95mv 1 a r sw(fbsw) fbsw switch on-resistance 10 v diode schottky diode forward voltage idiode = 100ma, t a = +25c 600 850 mv ovp overvoltage protection isl97634irt14z 14 v isl97634irt18z 18 v isl97634irt26z 26 28 v vil logic low voltage of pwm/en 0.6 v vih logic high voltage of pwm/en 1.5 v isl97634
3 fn6264.2 april 10, 2007 block diagram pin description pin number pin name description 1 gnd ground pin. connect to local ground. 2 vin input supply pin. connect to the input supply voltage , the inductor and the input supply decoupling capacitor. 3 pwm/en pwm or enable pin. connect ex ternal pwm signal allows pulse width modulation current operation. enable signal allows peak current operation or disable signal shuts down the device. 4 nc no connect 5 fb feedback pin. connect the sense resistor between fb and ground. the cathode of bottom led can also be connected at this pin if the output current is not to be pwmed. 6 fbsw fb disconnect switch. connect to the cathode of the bottom led if the output current to be pwmed. 7 vout output pin. connect to the anode of the top led and the output filter capacitor. 8 lx switching pin. connect to inductor. fet pwm logic controller gm amplifier 95mv gm amp compensation pwm comparator vin pwm/en lx gnd fb rset cout l vin (2.4v to 5.5v) 2 leds to 6 leds cin isl97634 vout bandgap reference generator fbsw pwm/en driver gm amp compensation current sense 1.4mhz oscillator and ramp generator isl97634
4 fn6264.2 april 10, 2007 typical performance curves figure 1. efficiency vs pwm duty cycle figure 2. quiescent current vs v in (pwm/en = hi) figure 3. load regulation (v in = 4v) figure 4. line regulation figure 5. dimmng linearity (fb voltage) vs duty cycle figure 6. pwm dimming at 1khz, d = 1% 50 55 60 65 70 75 80 85 90 0 20406080100 efficiency (%) pwm duty cycle (%) 3 leds, 10h 3 leds, 22h 6 leds, 10h 6 leds, 22h 4 leds, 10h v in = 4v rset = 4 f pwm = 1khz iled_peak = 25ma -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0246 i q (ma) 135 v in (v) 19.92 19.96 20.00 20.04 20.08 0 5 10 15 20 25 30 i o (ma) v out (v) 19.62 19.64 19.66 19.68 19.70 19.72 19.74 19.76 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v in (v) i o (ma) 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 duty cycle (%) 6 leds vin = 4v rset = 4 l = 10h fb voltage (mv) 20khz 32khz 1khz iled pwm/en lx v out v in = 4v r1 = 4 l1 = 22h isl97634
5 fn6264.2 april 10, 2007 detailed description the isl97634 uses a constant frequency, current mode control scheme to provide excellent line and load regulation. there are three ov p models for driving 3, 4, and 6 leds and their ovp thresholds are set at 14v, 18v, and 26v respectively. t he isl97634 operates from an input voltage of 2.4v to 5.5v and ambient temperature from -40c to +85c. the switching frequency is around 1.45mhz and allows the driver circuit to employ small lc components. the peak forward current of the led is set using the r set resistor. in the steady state mode, the led peak current is given by the following equation: pwm dimming the isl97634?s pwm/en pin can be tied permanently to high for a fixed current opera tion. on the other hand, the isl97634 can be applied with an external pwm signal to pulse width modulated the output current. it is well understood that the led brightness is a linear function of the led current. in addition, the average led current corresponds to the duty cycl e ?d? of the pwm signal as: as a result, pwm signal provides a means to dim the led brightness. pwm dimming offe rs the best leds matching over dc dimming. it is because the led peak current operating point is far away fr om the knee of the diode i-v curve where part to part variations are high. the pwm dimming test results are shown in figure 6 with two pwm frequencies, 1khz and 20khz. the vertical scale parameter fb is proportional to the current and therefore the brightness. for the isl97634, pwm dimming provides linear dimming adjustment with low frequency signal, such as 1khz and below. the applied pwm dimming signal can be up to 32khz figure 7. pwm dimming at 1khz, d = 1% zoom in figure 8. pwm dimming at 1khz, d = 99% figure 9. pwm dimming at 20khz, d = 50% iled pwm/en lx v out v in = 4v r1 = 4 l1 = 22h iled pwm/en lx v out v in = 4v r1 = 4 l1 = 22h iled pwm/en lx v out v in = 4v l1 = 22h r1 = 4 i led v fb r set --------------- = (eq. 1) i led avg ? v fb r set --------------- d ? = (eq. 2) isl97634
6 fn6264.2 april 10, 2007 ; however, the dimming linearity is compromised at low duty cycles as their durations are too short for the isl97634?s control loop to respond properly. this non ideality behavior does not cause any functional problem. the pwm dimming linear responses in figure 5 are expanded in figure 10. at 1khz pwm dimming, the duty cycle can virtually vary from below 1% to dc. on the other hand, at 20khz pwm dimming, the linearity range is from 5% to dc only. the low level non-linearity effects at high frequency pwm dimming is also reflected in the efficiency measurements in figure 11. feedback disconnect switch the isl97634 functions properly without using the fbsw. however, the output capacitor will discharge during the pwm off time resulting in poor dimming linearity at low duty cycles. the output discharge effect can be seen in figure 12. moreover, the output is modulated by the pwm signal that may create interference to other systems. . the fbsw should be used for pwm dimming as illustrated in ?typical application circuit? on page 1. during the pwm off time, the fbsw is opened. the leds are floating and therefore the output capacitor has no path to discharge. the led current responds accurately with the pwm signal (see figure 13). the output switches very quickly to the target current with minimal settling ringing and without being modulated by the pwm signal and therefore minimizes any system disturbance. overvoltage protection the isl97634 comes with overvoltage protection. the ovp trip points are at 14v, 18v, and 26v for isl97634irt14z, isl97634irt18z, and isl97634irt26z respectively. the maximum numbers of leds and ovp threshold are shown in table 1. when the device reac hes the ovp, the lx stops switching, disabling the boost circuit until v out falls about 7% below the ovp threshold. at this point, lx will be allowed to switch again. the ovp event will not cause the device to shutdown. there are three ovp options so that the 3 leds application should use the 14v ovp device and the 6 leds application should use the 26v ovp device. an output capacitor that is only rated for the required voltage range can therefore be used, whic h will optimize the component costs in some cases. figure 10. dimming linearity vs duty cycles zoom in 0 1 2 3 4 5 6 7 8 9 10 024681012 duty cycle (%) 6 leds v in = 4v rset = 4 l = 10h fb voltage (mv) 20khz 32khz 1khz figure 11. efficiency vs pwm dimming frequencies 50 55 60 65 70 75 80 85 90 0 5 10 15 20 25 30 iled (ma) efficiency (%) v in = 4v rset = 4 l = 22h 3 leds iled pwm/en lx v out v in = 4v r1 = 4 l1 = 22h figure 12. pwm dimming at 1khz without using fbsw figure 13. pwm dimming at 1khz using fbsw iled pwm/en lx v out v in = 4v r1 = 4 l1 = 22h isl97634
7 fn6264.2 april 10, 2007 shutdown when pwm/en is taken low the isl97634 enters into the power down mode where the supply current is reduced to less than 1a. the device resumes normal when the pwm/en goes high. components selection the input capacitance is typically 0.22f. the output capacitor should be in the range of 0.22f to 1f. x5r or x7r type of ceramic capacitors of the appropriate voltage rating are recommended. when choosing an inductor, make sure the average and peak current ratings are adequate by using the following formulas (80% efficiency assumed): where: ? i l is the peak-to-peak inductor current ripple in amps ? l is the inductance in h. ?f osc is the switching freq uency, typically 1.45mhz the isl97634 supports a wide range of inductance values (10h~82h). for lower inductor values or lighter loads, the boost inductor current may become discontinuous. for high boost inductor values, the boost inductor current will be in continuous mode. in addition to the inductor value and switching frequency, the input voltage, number of le ds and the led current also affects whether the converter operates in continuous conduction or discontinuous conduction mode. both operating modes are allowed and normal. the discontinuous conduction mode yields lower efficiency due to higher peak current. compensation the product of the output capacitor and the load create a pole while the inductor creates a right half plane zero. both of these attributes degrade the phase margin but the isl97634 has internal compensation network that ensures the device operates reliably un der the specified conditions. the internal compensation and the highly integrated functions of the isl97634 make it a design friendly device to be used in high volume, high reliability applications. applications analog dimming analog dimming is usually not recommended because of the brightness non-linearity at low levels dimming. however, some systems are emi or noise sensitive th at analog dimming may be more suitable than pwm dimming under those situations. the isl97632 is part of the same family as the isl97634 and has been designed with a serial interface to give access to 32 separate dimming levels. alternatively analog dimming can be achieved by applying a variable dc voltage (v dim ) at fb pin (see figure 14) to adjust the led current. as the dc dimming signal voltage increases above vfb, the voltages drop on r1 and r2 increase and the voltage drop on rset decreases. thus, the led current decreases. if v dim is taken below fb, the inverse will happen and the brightness will increase. the dc dimming signal voltage can be a variable dc voltage from a pot, a dcp (digitally controlled potentiometer), or a dc voltage generated by filtering a high frequency pwm control signal. as brightness is directly proportional to led currents, v dim may be calculated for any desired ?relative brightness? (f) using equation 7: where f = i led (dimmed)/i led (undimmed). these equations are valid for values of r1 and r2 such that both r1>>rset and r2>>rset. table 1. part no. ovp max no. of leds max iled isl97634irt14z 14v 3 70ma isl97634irt18z 18v 4 50ma isl97634irt26z 26v 6 30ma i lavg i led v out ? 0.8 v in ? --------------------------------- = (eq. 3) i lpk i lavg 1 2 -- - i l ? + = (eq. 4) i l v in v out v in ? () ? lv out f osc ?? -------------------------------------------------- - = (eq. 5) i led v fb r 1 r 2 + () v dim r 1 ? ? ? r 2 r ? set ------------------------------------------------------------------------- - = (eq. 6) figure 14. analog dimming control application circuit isl97634 c1 v in lx pwm fb gnd l1 22h c2 0.22f r set 4.75 leds 1f lx v in 3.3v r1 r2 v dim v out 3.3k v dim r 2 r 1 ------ - v fb 1 r 1 r 2 ------ - f ? + ?? ?? ?? ?? = (eq. 7) isl97634
8 fn6264.2 april 10, 2007 the analog dimming circuit can be tailored to a desired relative brightness for different v dim ranges using equation 8. where v dim_max is the maximum v dim voltage and f min is the minimum relative brightness (i.e., the brightness with v dim_max applied). i.e., v dim_max = 5v, f min = 10% (i.e., 0.1), r 2 = 189k i.e., v dim_max = 1v, f min = 10% (i.e., 0.1), r 2 = 35k efficiency improvement figure 1 shows the efficiency measurements during pwm operation. the choice of the inductor has a significant impact on the power efficiency. as shown in equation 4, the higher the inductance, the lower the peak current therefore the lower the conduction and switching losses. on the other hand, it has also a higher series resistance. nevertheless, the efficiency improvement effect by loweri ng the peak current is greater than the resistance increases wi th larger value of inductor. efficiency can also be improved for systems that have high supply voltages. since the isl 97634 can only supply from 2.4v to 5.5v, v in must be separated from the high supply voltage for the boost circuit as shown in figure 15 and the efficiency improvement is shown in figure 16. . 8 leds operation for medium size lcds that need more than 6 low power leds for backlighting, such as a portable media player or automotive navigation panel displays, the voltage range of the isl97634 is not suffici ent. however, the isl97634 can be used as an led controller with an external protection mosfet connected in cascode fashion to achieve higher output voltage. a conceptual 8 leds driver circuit is shown in figure 17. a 60v logic level n-channel mosfet is configured such that its drai n ties between the inductor and the anode of schottky diode, its gate ties to the input, and its source ties to the isl97634 lx node connecting to the drain of the internal switch. when th e internal switch turns on, it pulls the source of m1 down to ground, and lx conducts as normal. when the internal switch turns off, the source of m1 will be pulled up by the follower action of m1, limiting the maximum voltage on the isl97634 lx pin to below vin, but allowing the output voltage to go much higher than the breakdown limit on the lx pin. the switch current limit and maximum duty cycle will not be c hanged by this setup, so input voltage will need to be carefully considered to make sure that the required output voltage and current levels are achievable. because the source of m1 is effectively floating when the internal lx switch is off, the drain-to-source capacitance of m1 may be sufficient to capacitively pull the node high enough to breaks down the gate oxide of m1. to prevent this, vout should be connected to vin, allowing the internal schottky to limit the peak voltage. this will also hold the vout pin at a known low voltage, preventing the built in ovp function from causing problems. this ovp function is effectively useless in this mode as the real output voltage is outside its intended range. if the user wants to implement their own ovp protection (to pr event damage to the output capacitor, they should insert a zener from vout to the fb pin. in this setup, it would be wise not to use the fbsw to fb switch as otherwise the zene r will have to be a high power one capable of dissipating the entire led load power. then the led stack can then be conne cted directly to the sense resistor and via a 10k resistor to fb. a zener can be placed from vout to the fb pin allowing an over voltage event to pull up on fb with a low breakdown current (and thus low power zener) as a result of the 10k resistor. r 2 v dim_max v fb ? () r 1 ? [] v fb 1f min ? () ? [] ------------------------------------------------------------------- = (eq. 8) figure 15. separate high input voltage for higher efficiency operation vs = 12v l1 22 1 2 r1 4 c3 0.22 d2 d3 d1 d5 d6 d4 isl97634 fbsw lx vout pwm / en vin fb gnd c1 1 c2 0.1 v in = 2.7v to 5.5v figure 16. efficiency improvement with 9 and 12v inputs v s = 9v v s = 12v 0 5 10 15 20 25 30 iled (ma) efficiency (%) 90 85 80 75 70 v in = 4v 6 leds l1 = 22h r1 = 4 f pwm isl97634
9 fn6264.2 april 10, 2007 sepic operation for applications where the output voltage is not always above the input voltage, a buck or boost regulation is needed. a sepic (single ended primary inductance converter) topology, shown in figure 18, can be considered for such application. a single cell li-ion battery operating a cellular phone backlight or flashlight is one example. the battery voltage is between 2.5v and 4.2v, depending on the state of charge. on the othe r hand, the output may require only one 3v to 4v medium power led for illumination because the light guard of the backlight assembly is optimized for cost efficiency trade-off reason. in fact, a sepic configured led driver is flexible enough to allow the output to be well above or below the input voltage, unlike the previous example. another example is when the number of leds and input requirements are different from platform to platform, a common circuit and pcb that fit all the platforms in some cases may be beneficial enough that it outweighs the disadvantage of adding additional component cost. l1 and l2 can be a coupled inductor in one package. the simplest way to understand sepic topology is to think about it as a boost regulator where the input voltage is level shifted downward at the same magnitude and the lowest reference level starts at -v in rather than 0v. the sepic works as follows; assume the circuit in figure 18 operates normally, when the isl97634 internal switch opens and it is in the pwm off state, after a short duration where few lc time constants elapsed, the circuit is considered in the steady-state within the pwm off period that l1 and l2 are shorted. v b is therefore shorted to the ground and c3 is charged to v in with v a = v in . when the isl97634 internal switch closes and the circuit is in the pwm on state, v a is now pulled to ground. since the voltage in c3 cannot be changed instantaneously, therefore v b is shifted downward and becomes -v in . the next cycle when the isl97634 switch opens, v b boosts up to the targeted output like the standard boost regulator operation, except the lowest reference point is at -v in . the output is approximated as: where d is the on-time of the pwm duty cycle. the convenience of sepic comes with some trade off in addition to the additional l and c costs. the efficiency is usually lowered because of the relatively large efficiency loss through the schottky diode if the output voltage is low. the l2 series resistance also contributes additional loss. figure 19 shows the efficiency measurement of a single led application as the input varies between 2.7v and 4.2v. note v b is considered the level-shifted lx node of a standard boost regulator. the higher the input voltage, the lower the v b voltage will be during pwm on period. the result is that the efficiency will be lower at higher input voltages because the sepic has to work harder to boost up to the required level. this behavior is the opposite to the standard boost regulator?s and the comparison is shown in figure 19. pcb layout considerations the layout is very important for the converter to function properly. r set must be located as close as possible to the fb and gnd pins. longer traces to the leds are acceptable. similarly, the supply decouplin g cap and the output filter cap should be as close as possible to the v in and v out pins. the heat of the ic is mainly dissipated through the thermal pad of the package. maximizing the copper area connected to this pad if possible. in addition, a solid ground plane is always helpful for the emi performance. figure 17. conceptual 8 leds high voltage driver vout lx isl97634 pwm/en vin fbsw gnd fb r1 6.3 d3 d4 d5 d6 d7 d8 l1 2.2 12 v in = 2.7v to 5.5v c3 4.7 d0 10bq100 m1 fqt13n06l d1 c1 1 sk011c226kar c2 0.1 d2 figure 18. sepic led driver c1 1 l1 22 1 2 v a v b v in = 2.7v to 5.5v 22 l2 c3 1 c4 0.22 d1 r1 1 c2 0.1 vin sdin lx vout fbsw fb gnd isl97634 d0 v out v in d 1d ? () ------------------ = (eq. 9) 0 5101520 iled (ma) efficiency (%) 76 72 68 64 60 1 led l1 = l2 = 22h c3 = 1f r1 = 4.7 figure 19. efficiency measurement of a single led sepic driver v in = 4.2v v in = 2.7v isl97634
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6264.2 april 10, 2007 isl97634 thin dual flat no-lead plastic package (tdfn) // nx (b) section "c-c" 5 (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a m c n-1 12 plane seating c a a3 nx b d2/2 nx k for even terminal/side terminal tip c l e l c c l8.2x3a 8 lead thin dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.32 5,8 d 2.00 bsc - d2 1.50 1.65 1.75 7,8 e 3.00 bsc - e2 1.65 1.80 1.90 7,8 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n 8 2 nd 4 3 rev. 0 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389.
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